Kathmandu, May 27: Huawei has introduced a new semiconductor development principle called the Tau (τ) Scaling Law, positioning it as a possible alternative to the decades-old Moore’s Law as the global chip industry faces growing physical and economic limitations.
The announcement was made by He Tingbo during a keynote speech titled “New Semiconductor Path in Practice” at the IEEE International Symposium on Circuits and Systems held in Shanghai.
According to Huawei, the new framework shifts the focus of semiconductor advancement from shrinking transistor size to reducing signal propagation delay across devices, circuits, chips, and computing systems. The company said this “time scaling” approach could help sustain chip performance improvements as traditional geometric scaling reaches its limits.
Huawei also introduced a new architecture called Logic Folding, which aims to shorten wiring paths inside chips and improve transistor density and energy efficiency. The company said its upcoming Kirin chips, scheduled for release in Fall 2026, will be the first to adopt the new architecture.
The Chinese tech giant further claimed that it has already designed and mass-produced 381 chips based on the Tau Scaling framework over the past six years for use in smartphones, artificial intelligence, and other sectors.
Huawei projected that by 2031, its high-end chips could achieve transistor density equivalent to 1.4-nanometer processes, although industry analysts note that the claim refers to density equivalence rather than actual 1.4nm manufacturing capability.
The development comes as Huawei continues efforts to reduce dependence on foreign semiconductor technologies amid ongoing U.S. restrictions on advanced chipmaking equipment and technologies.
